1. Field of the Invention
Embodiments of the present invention relate to a semiconductor package having a low profile.
2. Description of the Related Art
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.
While a wide variety of packaging configurations are known, flash memory storage cards may in general be fabricated as system-in-a-package (SiP) or multichip modules (MCM), where a plurality of die are mounted on a substrate. The substrate on which the die are mounted may in general include a rigid, dielectric base having a conductive layer etched on one or both sides. The one or more semiconductor die and/or passive components such as resistors, inductors and/or capacitors may be mounted to the substrate by surface mount technology (SMT). SMT is a known method of soldering die and/or surface mounted components to plated portions of conductive layers on the surface of the substrate. The conductive layer(s) provide an electric lead structure for communication between the die, passive components and an external electronic system. Once electrical connections between the surface mounted components and substrate are made, the assembly is then typically encased in a molding compound to form a protected semiconductor package.
FIG. 1 is a top view of a conventional substrate 20 including areas 22 for receiving a component affixed to the substrate in a known SMT process. FIGS. 2 and 3 are enlarged top and side views, respectively, of the substrate area 22. The substrate area 22 in general includes a rigid core 26, of for example polyimide laminate. Thin film conductive layers 28 may be formed on the core in a desired conductance pattern using known photolithography and etching processes. Portions of the conductance pattern may be plated with a thin layer 30 of gold or other highly resistive metal. The substrate area 22 may then be coated with a solder mask 34 (shown only in FIG. 3) to insulate and protect the electrical lead pattern defined on the substrate.
Solder paste 32 may be applied to the plated layer 30, and a component 36 then set atop the solder paste, as indicated in FIG. 3. The solder paste holds the passive component in position while the substrate is heated in a solder reflow process to harden the solder, thereby securing the component 36 to the plated layer 30 and electrically connecting the component to the substrate.
Once the die and/or passive components are mounted to the substrate, the package may be encapsulated in a molding compound to form a finished semiconductor package. The thickness of the encapsulated package may be approximately 0.65 mm, but different packages may have different thicknesses. There is an ever-present drive to decrease the overall dimensions of conventional semiconductor packages, including package thickness. However, if the thickness of the molding compound were reduced in conventional packages, there is a risk of exposing the components mounted to the substrate. In addition to the height of the passive components, the conductance pattern, plated layer and solder paste on which the passive components are mounted all add to the thickness of the semiconductor package. In conventional packages, the conductance pattern, plated layer and solder paste may add approximately 50 microns (μm) to the thickness of a semiconductor package.